Stabilization of flatband voltages and threshold voltages in hafnium oxide based silicon transistors for cmos

ABSTRACT

The present invention provides a metal stack structure that stabilizes the flatband voltage and threshold voltages of material stacks that include a Si-containing conductor and a Hf-based dielectric. This present invention stabilizes the flatband voltages and the threshold voltages by introducing a rare earth metal-containing layer into the material stack that introduces, via electronegativity differences, a shift in the threshold voltage to the desired voltage. Specifically, the present invention provides a metal stack comprising:
         a hafnium-based dielectric; a rare earth metal-containing layer located atop of, or within, said hafnium-based dielectric; an electrically conductive capping layer located above said hafnium-based dielectric; and a Si-containing conductor.

RELATED APPLICATION

This application is a continuation application of U.S. Ser. No.11/118,521, filed Apr. 29, 2005.

FIELD OF THE INVENTION

The present invention generally relates to a semiconductor structure,and more particularly to a material stack useful in metal oxidesemiconductor capacitors (MOSCAPs) and metal oxide semiconductor fieldeffect transistors (MOSFETs) that includes a rare earth metal (or rareearth-like)-containing layer present on top of, or within, a dielectriclayer which is capable of stabilizing the threshold voltage and flatbandvoltage of a Si-containing conductor. Specifically, the presence of therare earth metal (or rare earth-like)-containing layer induces a bandbending in a semiconductor substrate so as to shift the thresholdvoltage to more negative values than when such a layer is not used.

BACKGROUND OF THE INVENTION

In standard silicon complementary metal oxide semiconductor (CMOS)technology, n-type field effect transistors (pFET) use an As (or otherdonor) doped n-type polysilicon layer as a gate electrode that isdeposited on top of a silicon dioxide or silicon oxynitride gatedielectric layer. The gate voltage is applied through this polysiliconlayer to create an inversion channel in the p-type silicon underneaththe gate oxide layer.

In future technology, silicon dioxide or silicon oxynitride dielectricswill be replaced with a gate material that has a higher dielectricconstant. These materials are known as “high k” materials with the term“high k” denoting an insulating material whose dielectric constant isgreater than 4.0, preferably greater than about 7.0. The dielectricconstants mentioned herein are relative to a vacuum unless otherwisespecified. Of the various possibilities, hafnium oxide, hafniumsilicate, or hafnium silicon oxynitride may be the most suitablereplacement candidates for conventional gate dielectrics due to theirexcellent thermal stability at high temperatures.

Silicon metal oxide semiconductor field effect transistors (MOSFETs)fabricated with a hafnium-based dielectric as the gate dielectric sufferfrom a non-ideal threshold voltage when n-MOSFETs are fabricated. Todate, there is no known viable solution that can be used to solve theaforementioned problem that exists with Si MOSFETs that include aHf-based dielectric.

In view of the above-mentioned problem with prior art Si MOSFETs thatinclude a Hf-based dielectric, there is a need for providing a methodand structure that is capable of stabilizing the flatband voltages andthreshold voltages in MOSFETs that contain a Hf-based gate dielectric.

SUMMARY OF THE INVENTION

The present invention provides a metal stack structure that stabilizesthe flatband voltages and threshold voltages of material stacks thatinclude a Si-containing conductor and a Hf-based dielectric. It isemphasized that prior art Si MOSFETs fabricated with hafnium oxide asthe gate dielectric suffers from a non-ideal threshold voltage whenn-MOSFETs are fabricated. This present invention solves this problem byintroducing a rare earth metal-containing layer into the material stackthat introduces, via electronegativity differences, a shift in thethreshold voltage to the desired voltage.

In broad terms, the present invention provides a material stackcomprising:

a hafnium-based dielectric;

a rare earth metal-containing layer located atop of, or within, saidhafnium-based dielectric;

an electrically conducting capping layer located above saidhafnium-based dielectric; and

a Si-containing conductor.

In some embodiments of the present invention, an optional chemox layercan be located beneath the Hf-based dielectric. As used throughout theinstant application, the term “chemox layer” denotes an optionalinterfacial dielectric that is formed on the surface of a semiconductorsubstrate prior to forming the Hf-based dielectric. It is noted that theterm “rare earth metal-containing layer” is used herein to denote rareearth materials as well as materials that behave as a rare earthmaterial.

In yet another embodiment of the present invention, a material stackincluding an optional chemox layer, HfO₂ or Hf silicate as said Hf-baseddielectric, a metal nitride layer including at least one rare earthmetal or rare earth-like material, and polySi as the Si-containing gateconductor, wherein said metal nitride layer is used as both said rareearth-containing layer and said electrically conducting capping layer isprovided.

It is noted that the presence of the rare earth metal-containing layerin the inventive material stack introduces a charge center into theHf-based dielectric which has an electronegativity and/or valence thatis different from the Hf-based dielectric layer. Specifically, thepresence of the rare earth metal-containing layer in the inventivematerial stack introduces foreign atoms into the Hf-based dielectricthat may residue either at substitutional or interstitial sites on theHf-based dielectric. By altering the defect chemistry, the chargecenters alter the electrostatic profile in the material stack, and theeffective alignments of the potential in the dielectric and the vicinityof the interfaces between the Hf-based dielectric and the silicon andelectrode sandwiching the dielectric. It is noted that the rare earthmetal-containing layer may remain as a separate layer or it mayinterdiffuse within the Hf-based dielectric. The location of the rareearth metal-containing layer within the Hf-based dielectric is notcritical so long as there is a concentration gradient of the rare earthmetal-containing layer present in, or on, the Hf-based dielectric. Theconcentration gradient may be abrupt or non-abrupt.

In addition to the material stack described above, the present inventionalso provides MOSCAP and MOSFET structures which include the inventivematerial stack as a component. Specifically, and in broad terms, thepresent invention provides a semiconductor structure that comprises:

a patterned material stack located on a surface of a semiconductorsubstrate, said patterned material stack comprising a hafnium-baseddielectric; a rare earth metal-containing layer located atop of, orwithin, said hafnium-based dielectric; an electrically conductivecapping layer located above said hafnium-based dielectric; and aSi-containing conductor.

The present invention also relates to a method of fabricating theinventive material stack as well as methods of fabricating asemiconductor structure that includes the same.

It is observed that the inventive material stack provides a negativeshift in the flatband voltage (as compared to a standard material stackthat does not include the rare earth metal-containing layer) such thatthe flatband voltage is now appropriate for the fabrication of annMOSFET. In an ideal n-channel MOSFET, the electrode is such that itsFermi level is aligned with the conduction band of the Si substrate. Inthe past, the problem has been that a practical semiconductor devicecould not be built with such an alignment and consequently the flatbandvoltage was greater than +0.1 V instead of −0.2 V, which is typical ofsuch flatband voltages for Si substrates with standard doping. Using theabove described material stack, the flatband voltage is about −0.15 V toabout 0.05 V. Such a flatband voltage translates to a threshold voltage(the voltage at which the transistor turns on) to about 0.1 V for ann-channel MOSFET, which is the desired value. The prior material stacknot including the rare earth metal-containing layer results in highelectron channel mobilities (on the order of about 200 cm²/Vs at anelectric field of 1 MV/cm) at low inversion electrical thickness (on theorder of about 14-15 Å). However, the prior art material stack does notdeliver the necessary threshold voltages for nMOSFETs. The desiredthreshold voltage, without compromising the other specifications, isachieved using the inventive material stack.

There are several unique aspects of the inventive material stack thatshould be briefly discussed. First, the presence of the rare earthmetal-containing layer introduces a dipole into the dielectric stack.The origin of the dipole is due to the strongly electropositive natureof the rare earth metal atom. The sheet of rare earth metal atoms drawsa positive charge towards it, resulting in a dipole. Without wishing tobe bound by any theory, it is believed that this dipole creates thedesired shift in flatband voltage and threshold voltage. Thermalprocesses diffuse the rare earth metal atoms across the gate stack.However, such a dipole will result as long as there is a non-symmetricaldistribution in the rare earth metal composition across the stack,regardless of whether the rare earth metal composition in the stack isatomically abrupt or diffused, Second, the presence of the rare earthmetal atoms in the Hf-based dielectric (due to interdiffusion) willresult in a charge compensated dielectric. It is known that positivelycharged oxygen vacancies play a role in flatband voltage determinationin an ionic oxide such as hafnium oxide.

If a small quantity of rare earth metal is present, the rare earth metalion substituting for Hf ion acts as a negatively charged defect (RE_(Hf)₋ ). Due to needs for charge neutrality, the presence of the rare earthmetal substitutional defect can raise the concentration of the chargedoxygen vacancies, thereby promoting the necessary flatband voltageshift. Thirdly, via its strong electropositive nature, the rare earthmetal atom will modify the interface chemistry at thesemiconductor/chemox/Hf-based dielectric interfacial region and the topHf-based dielectric/rare earth metal-containing/electrically conductivecapping layer region altering the effective alignment of theworkfunctions of the material stack. In essence, all three of theaforementioned phenomena are the consequence of insertion of a highlyelectropositive element as a distinct layer in the stack sequence. Thisdistinct layer then can interdiffuse, but the presence of a compositionprofile for this electropositive element ensures the flatband/thresholdvoltage.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A-1D are pictorial representations (through cross sectionalviews) illustrating the basic processing steps that are employed in thepresent invention for forming a material stack of the present invention.

FIG. 2A is a pictorial representation (through a cross sectional view)illustrating a MOSCAP structure that can be formed from the inventivematerial stack; and FIG. 2B is a pictorial representation (through across sectional view) illustrating a MOSFET structure that can be formedfrom the inventive material stack.

FIG. 3 is a graph including CV (capacitance vs. voltage) curvescomparing HfO₂/La₂O₃/TiN/PolySi stacks with typical HfO₂/TiN/PolySistacks after 1000° C.+500° forming gas anneal.

FIG. 4 is a graph plotting the CV of the inventive material stack ascompared to ideal bandedge position.

FIG. 5 is the IV curve of the inventive material stack showing that theinventive stack can be used in providing a low leakage nMOSCAP device.

DETAILED DESCRIPTION OF THE INVENTION

The present invention, which provides a material stack useful in MOSCAPsand MOSFETs that includes a rare earth metal-containing layer present ontop of, or in, a dielectric layer which is capable of stabilizing thethreshold voltage and flatband voltage of a Si-containing conductor,will now be described in greater detail by referring to the followingdiscussion and drawings that accompany the present application. It isnoted that the drawings of the present application are provided forillustrative purposes and thus they are not drawn to scale.

It is again emphasized that prior art Si MOSFETs fabricated with hafniumoxide as the gate dielectric suffer from a non-ideal threshold voltagewhen n-MOSFETs are fabricated. This present invention solves thisproblem by introducing a rare earth metal-containing layer into thematerial stack that introduces, via electronegativity differences, ashift in the threshold voltage to the desired voltage. Although Hf-baseddielectrics are specifically described and illustrated, the presentinvention can also be used when the Hf-based dielectric is replaced, orused in communication, with another dielectric material having adielectric constant of greater than about 4.0.

The material stack of the present invention together with the processingsteps that are used in forming the same will be described first followedby a description of the same as a component of a MOSCAP and a MOSFET. Itis noted that although the MOSCAP and the MOSFET are shown as separatestructures, the present invention also contemplates structures whichinclude both the MOSCAP and the MOSFET on a surface of a singlesemiconductor substrate.

Reference is first made to FIGS. 1A-1D which are pictorialrepresentations (through cross sectional views) depicting the basicprocessing steps that are used in forming the inventive material stackon the surface of a semiconductor substrate. FIG. 1A shows an initialstructure that is formed in the present invention that includes asemiconductor substrate 10, an optional chemox layer 12 on a surface ofthe semiconductor substrate 10 and a Hf-based dielectric 14 that islocated on the optional chemox layer 12. When the chemox layer 12 is notpresent, the Hf-based dielectric 14 is located on a surface of thesemiconductor substrate 10.

The semiconductor substrate 10 of the structure shown in FIG. 1Acomprises any semiconducting material including, but not limited to: Si,Ge, SiGe, SiC, SiGeC, Ge, GaAs, GaN, InAs, InP and all other III/V orII/VI compound semiconductors. Semiconductor substrate 10 may alsocomprise an organic semiconductor or a layered semiconductor such asSi/SiGe, a silicon-on-insulator (SOI), a SiGe-on-insulator (SGOI) orgermanium-on-insulator (GOI). In some embodiments of the presentinvention, it is preferred that the semiconductor substrate 10 becomposed of a Si-containing semiconductor material, i.e., asemiconductor material that includes silicon. The semiconductorsubstrate 10 may be doped, undoped or contain doped and undoped regionstherein. The semiconductor substrate 10 may include a single crystalorientation or it may include at least two coplanar surface regions thathave different crystal orientations (the latter substrate is referred toin the art as a hybrid substrate). When a hybrid substrate is employed,the nFET is typically formed on a (100) crystal surface, while the pFETis typically formed on a (110) crystal plane. The hybrid substrate canbe formed by techniques that are well known in the art.

The semiconductor substrate 10 may also include a first doped (n- or p-)region, and a second doped (n- or p-) region. For clarity, the dopedregions are not specifically shown in the drawing of the presentapplication. The first doped region and the second doped region may bethe same, or they may have different conductivities and/or dopingconcentrations. These doped regions are known as “wells” and they areformed utilizing conventional ion implantation processes.

At least one isolation region (not shown) is then typically formed intothe semiconductor substrate 10. The isolation region may be a trenchisolation region or a field oxide isolation region. The trench isolationregion is formed utilizing a conventional trench isolation process wellknown to those skilled in the art. For example, lithography, etching andfilling of the trench with a trench dielectric may be used in formingthe trench isolation region. Optionally, a liner may be formed in thetrench prior to trench fill, a densification step may be performed afterthe trench fill and a planarization process may follow the trench fillas well. The field oxide may be formed utilizing a so-called localoxidation of silicon process. Note that the at least one isolationregion provides isolation between neighboring gate regions, typicallyrequired when the neighboring gates have opposite conductivities, i.e.,nFETs and pFETs. The neighboring gate regions can have the sameconductivity (i.e., both n- or p-type), or alternatively they can havedifferent conductivities (i.e., one n-type and the other p-type).

After processing the semiconductor substrate 10, a chemox layer 12 isoptionally formed on the surface of the semiconductor substrate 10. Theoptional chemox layer 12 is formed utilizing a conventional growingtechnique that is well known to those skilled in the art including, forexample, oxidation or oxynitridation. The chemox layer 12 is comprisedof silicon oxide, silicon oxynitride or a nitrided silicon oxide. Thethickness of the chemox layer 12 is typically from about 0.5 to about1.2 nm, with a thickness from about 0.8 to about 1 nm being moretypical.

In accordance with an embodiment of the present invention, the chemoxlayer 12 is a silicon oxide layer having a thickness from about 0.6 toabout 0.8 nm that is formed by wet chemical oxidation. The process stepfor this wet chemical oxidation includes treating a cleanedsemiconductor surface (such as a HF-last semiconductor surface) with amixture of ammonium hydroxide, hydrogen peroxide and water (in a 1:1:5ratio) at 65° C.

Next, a Hf-based dielectric 14 can be formed on the surface of thechemox layer 12, if present, or the surface of the semiconductorsubstrate 10 by a deposition process such as, for example, chemicalvapor deposition (CVD), plasma-assisted CVD, physical vapor deposition(PVD), metalorganic chemical vapor deposition (MOCVD), atomic layerdeposition (ALD), evaporation, reactive sputtering, chemical solutiondeposition and other like deposition processes. The Hf-based dielectric14 may also be formed utilizing any combination of the above processes.

The Hf-based dielectric 14 is comprised of hafnium oxide (HfO₂), hafniumsilicate (HfSiO_(x)) Hf silicon oxynitride (HfSiON) or multilayersthereof. In some embodiments, the Hf-based dielectric 14 comprises amixture of HfO₂ and ZrO₂. In other embodiments, the Hf-based dielectric14 can be replaced, or used in conjunction with, another dielectricmaterial having a dielectric constant of greater than about 4.0,typically greater than about 7.0. The other dielectrics are metal oxidesor mixed metal oxides that are well known to those skilled in the artand they can be formed utilizing any of the techniques described hereinin forming the Hf-based dielectric 14. Typically, the Hf-baseddielectric 14 is hafnium oxide or hafnium silicate. The Hf-baseddielectric 14 is a “high k” material whose dielectric constant isgreater than about 10.0.

The physical thickness of the Hf-based dielectric 14 may vary, buttypically, the Hf-based dielectric 14 has a thickness from about 0.5 toabout 10 nm, with a thickness from about 0.5 to about 3 nm being moretypical.

In one embodiment of the present invention, the Hf-based dielectric 14is hafnium oxide that is formed by MOCVD were a flow rate of about 70 toabout 90 mgm of hafnium-tetrabutoxide (a Hf-precursor) and a flow rateof O₂ of about 250 to about 350 sccm are used. The deposition of Hfoxide occurs using a chamber pressure between 0.3 and 0.5 Torr and asubstrate temperature of between 400° and 500° C.

In another embodiment of the present invention, the Hf-based dielectric14 is hafnium silicate which is formed by MOCVD using the followingconditions (i) a flow rate of the precursor Hf-tetrabutoxide of between70 and 90 mg/m, a flow rate of O₂ between 25 and 100 sccm, and a flowrate of SiH₄ of between 20 and 60 sccm; (ii) a chamber pressure between0.3 and 0.5 Torr, and (iii) a substrate temperature between 400° and500° C.

Once the structure shown in FIG. 1A is formed (with or without theoptional chemox layer 12), a rare earth metal-containing layer 16 isthen formed on the Hf-based dielectric 14 providing the structure shownin FIG. 1B. The rare earth metal-containing layer 16 comprises an oxideor nitride of at least one element from Group III of the Periodic Tableof Elements including, for example, La, Ce, Pr, Nd, Pm, Sm, Eu, Ga, Tb,Dy, Ho, Er, Tm, Yb, Lu or mixtures thereof. Preferably, the rare earthmetal-containing layer 16 comprises an oxide of La, Ce, Y, Sm, Er,and/or Tb, with La₂O₃ or LaN being most preferred.

The rare earth metal-containing layer 16 is formed utilizing aconventional deposition process including, for example, evaporation,molecular beam deposition, MOCVD, ALD, PVD and other like depositionprocesses.

In one embodiment of the present invention, the rare earthmetal-containing layer 16 is formed by placing the structure shown inFIG. 1A into the load-lock of a molecular beam deposition chamber,followed by pumping this chamber down to the range of 10⁻⁵ to 10⁻⁸ Torr.After these steps, the structure is inserted, without breaking vacuuminto the growth chamber where the rare earth metal-containing layer 16such as La oxide is deposited by directing atomic/molecular beams of therare earth metal and oxygen or nitrogen onto the structure's surface.Specifically, because of the low pressure of the chamber, the releasedatomic/molecular species are beamlike and are not scattered prior toarriving at the structure. A substrate temperature of about 300° C. isused. In the case of La₂O₃ deposition, the La evaporation cell is heldin the temperature range of 1400° to 1700° C., and a flow rate of 1 to 3sccm of molecular oxygen is used. Alternatively, atomic or excitedoxygen may be used as well, and this can be created by passing theoxygen through a radio frequency source excited in the range of 50 to600 Watts. During the deposition, the pressure within the chamber can bein the range from 1×10⁻⁵ to 8×10⁻⁵ Torr, and the La oxide growth ratecan be in the range from 0.1 to 2 nm per minute, with a range from 0.5to 1.5 nm being more typical.

The rare earth metal-containing layer 16 typically has a thickness fromabout 0.1 nm to about 3.0 nm, with a thickness from about 0.3 nm toabout 1.6 nm being more typical.

Next, and as shown in FIG. 1C, an electrically conducting capping layer18 is formed on the surface of the rare earth metal-containing layer 16utilizing a conventional deposition process. Examples of conventionaldepositions that can be used in forming the electrically conductivecapping layer 18 include CVD, PVD, ALD, sputtering or evaporation. Theelectrically conductive capping layer 18 is formed on the surface of therare earth metal-containing layer 16 utilizing a conventional depositionprocess in which the vacuum between depositions may or may not bebroken. The electrically conductive capping layer 18 comprises ametallic material and/or a semimetallic material that is capable ofconducting electrons. Specifically, the capping layer 18 is a metalliccapping layer such as a metal nitride or a metal silicon nitride. Theelectrically conductive capping layer 18 provides the functions of (a)protecting the rare earth metal-containing layer from the ambient, (b)acts a diffusion barrier to ambient oxygen, and (c) prevents reaction ofthe rare earth metal-containing layer with the Si-containing conductor.In the embodiment when the capping layer includes a metal, the metalcomponent of the capping layer 18 may comprise a metal from Group IVB orVB of the Periodic Table of Elements. Hence, the electrically conductivecapping layer 18 may include Ti, Zr, Hf, V, Nb or Ta, with Ti or Tabeing highly preferred. By way of example, the electrically conductivecapping layer 18 preferably comprises TiN or TaN. In addition to theaforementioned electrically conductive capping layer materials, thepresent invention also includes a ternary alloy of Ti—La—N, a ternaryalloy of Ta—La—N or a stack of a ternary alloy of Ti—La—N or Ta—La—Nthat is mixed with La₂O₃ or another one of the above mentioned rareearth metal-containing materials. If the later is used, it may bepossible to replace the separate rare earth metal-containing layer 16and the electrically conductive capping layer, with a single layerincluding both components.

For example and in yet another embodiment of the present invention, amaterial stack including an optional chemox layer, HfO₂ or Hf silicateas said Hf-based dielectric, a metal nitride layer including at leastone rare earth metal or rare earth-like material, and polySi as theSi-containing gate conductor, wherein said metal nitride layer is usedas both said rare earth-containing layer and said electricallyconducting capping layer is provided.

The physical thickness of the electrically conductive capping layer 18may vary, but typically, the electrically conductive capping layer 18has a thickness from about 0.5 to about 200 nm, with a thickness fromabout 5 to about 80 nm being more typical.

In one embodiment of the present invention, the electrically conductivecapping layer 18 is TiN that is deposited by evaporating Ti from aneffusion cell held in the range of 1550° to 1900° C., typically 1600° to1750° C., and using an atomic/excited beam of nitrogen that is passedthrough a remote radio frequency source. The substrate temperature canbe around 300° C. and the nitrogen flow rate can be between 0.5 sccm and3.0 sccm. These ranges are exemplary and by no way limit the presentinvention. The nitrogen flow rate depends upon the specifics of thedeposition chamber, in particularly, the pumping rate on the chamber.The TiN may be deposited, in other ways, as well, such as chemical vapordeposition or sputtering and the technique is not critical.

Following the formation of the electrically conductive capping layer 18as shown in FIG. 1C, a Si-containing conductor 20 is formed atop theelectrically conductive capping layer 18. The resultant structureincluding the Si-containing conductor 20 is shown in FIG. 1D.Specifically, a blanket layer of a Si-containing material is formed onthe electrically conductive capping layer 18 utilizing a knowndeposition process such as, for example, physical vapor deposition, CVDor evaporation. The Si-containing material used in forming the conductor20 includes Si or a SiGe alloy layer in either single crystal,polycrystalline or amorphous form. Combinations of the aforementionedSi-containing materials are also contemplated herein. The blanket layerof Si-containing material 20 may be doped or undoped. If doped, anin-situ doping deposition process may be employed in forming the same.Alternatively, a doped Si-containing layer can be formed by deposition,ion implantation and annealing. The ion implantation and annealing canoccur prior to or after a subsequent etching step that patterns thematerial stack. The doping of the Si-containing layer will shift theworkfunction of the gate conductor formed. Illustrative examples ofdopant ions for nMOSFETs include elements from Group VA of the PeriodicTable of Elements (Group IIIA elements can be used when pMOSFETs areformed). The thickness, i.e., height, of the Si-containing layer 20deposited at this point of the present invention may vary depending onthe deposition process employed. Typically, the Si-containing conductor20 has a vertical thickness from about 20 to about 180 nm, with athickness from about 40 to about 150 nm being more typical.

The gate stack structure shown in FIG. 1D can then be fabricated into aMOSCAP 50 as shown in FIG. 2A or a MOSFET 52 as shown in FIG. 2Butilizing conventional processes that are well known in the art. Each ofthe illustrated structures includes a material stack such as shown inFIG. 1D which has been at least patterned by lithography and etching.

The MOSCAP formation includes forming a thermal sacrificial oxide (notshown) on the surface of the semiconductor substrate. Using lithography,the active areas of the capacitor structure are opened in the fieldoxide by etching. Following the removal of the oxide, the material stackas shown in FIG. 1D is formed as described above. Specifically, thematerial stack was provided, patterned by lithography and etching, andthen the dopants are introduced into the Si-containing conductor 20. Thedopants are typically P (implant dose of 5E15 ions/cm² using an implantenergy of 12 keV). The dopants are activated using an activation annealthat is performed at 950° C. to 1000° C. for about 5 seconds. In somecases, a forming gas anneal (5-10% hydrogen) can follow which isperformed between 500° to 550° C. for chemox layer/semiconductorsubstrate interface state passivation.

The MOSFET formation includes first forming isolation regions within thesubstrate as described above. Similar to the MOSCAP and after removingthe sacrificial oxide, a material stack as described above is formed.Following patterning of the material stack, at least one spacer 24 istypically, but not always, formed on exposed sidewalls of each patternedmaterial stack. The at least one spacer 24 is comprised of an insulatorsuch as an oxide, nitride, oxynitride and/or any combination thereof.The at least one spacer 24 is formed by deposition and etching.

The width of the at least one spacer 24 must be sufficiently wide suchthat the source and drain silicide contacts (to be subsequently formed)do not encroach underneath the edges of the patterned material stack.Typically, the source/drain silicide does not encroach underneath theedges of the patterned material stack when the at least one spacer 24has a width, as measured at the bottom, from about 20 to about 80 nm.

The patterned material stack can also be passivated at this point of thepresent invention by subjecting the same to a thermal oxidation,nitridation or oxynitridation process. The passivation step forms a thinlayer of passivating material about the material stack. This step may beused instead or in conjunction with the previous step of spacerformation. When used with the spacer formation step, spacer formationoccurs after the material stack passivation process.

Source/drain diffusion regions 26 are then formed into the substrate.The source/drain diffusion regions 26 are formed utilizing ionimplantation and an annealing step. The annealing step serves toactivate the dopants that were implanted by the previous implant step.The conditions for the ion implantation and annealing are well known tothose skilled in the art. The source/drain diffusion regions 26 may alsoinclude extension implant regions which are formed prior to source/drainimplantation using a conventional extension implant. The extensionimplant may be followed by an activation anneal, or alternatively thedopants implanted during the extension implant and the source/drainimplant can be activated using the same activation anneal cycle. Haloimplants are also contemplated herein.

In some cases, a forming gas anneal (5-10% hydrogen) can follow which isperformed between 500° to 550° C. for chemox layer/semiconductorsubstrate interface state passivation.

The above processing steps form the structure shown in FIG. 2B. FurtherCMOS processing such as formation of silicided contacts (source/drainand gate) as well as formation of BEOL (back-end-of-the-line)interconnect levels with metal interconnects can be formed utilizingprocessing steps that are well known to those skilled in the art.

The following example is provided for illustrative purposes and thus itshould not be construed to limit the scope of the present application inany way.

EXAMPLE

In this example, an nMOSCAP was prepared utilizing a material stack ofthe present invention and it was compared with a prior art nMOSCAP whichdid not include the inventive material stack. Specifically, a materialstack comprising SiO₂/HfO₂/0.8 nm La₂O₃/30 nm TiN/PolySi stack(Inventive) was prepared utilizing the processing steps mentioned aboveand that material stack was used as a component of an nMOSCAP. A priorart material stack, not including La oxide was prepared and was used acomponent for a prior art nMOSCAP (Prior Art). Each material stack afterprocessing on a Si substrate was subjected to a 1000° C. rapid thermalanneal in nitrogen, followed by a 500° C. forming gas anneal.

FIG. 3 shows the CV curves of the two nMOSCAP. The CET (CapacitanceEquivalent Thickness) and the EOT (Equivalent Oxide Thickness) of theInventive material stack were 10.2 Å and 6.5 Å, respectively. The CETand the EOT of the Prior Art material stack were 14.7 Å and 10.5 Å,respectively.

The flatband voltage, which is characteristic of the threshold voltage,for the Inventive material stack is about 50-100 mV from ideal bandedgeposition for an n-doped polySi gate. For comparison, the Prior Artmaterial stack, which does not include the rare earth metal-containinglayer, was about 350 mV from ideal bandedge position. Another notableattribute was that extremely aggressive scaling obtained in theinventive devices (sub 1 nm EOTs) after high temperature annealing.

FIG. 4 shows a fit of the experimental CV of the Inventive materialstack to the ideal CV showing that the nMOSCAP including the materialstack of the present invention are well behaved. FIG. 5 shows the IVcurve of the inventive material stack showing that nMOSFETs includingthe same are well behaved devices that have low leakage.

While the present invention has been particularly shown and describedwith respect to preferred embodiments thereof, it will be understood bythose skilled in the art that the foregoing and other changes in formsand details may be made without departing from the spirit and scope ofthe present invention. It is therefore intended that the presentinvention not be limited to the exact forms and details described andillustrated, but fall within the scope of the appended claims.

1. An n-metal oxide semiconductor field effect transistor (n-MOSFET)material stack comprising: a hafnium-based dielectric; a rareearth-containing layer comprising an oxide or nitride of at least oneelement from Group IIIB of the Periodic Table of Elements located atopof; or within, said hafnium-based dielectric; an electrically conductingcapping layer located above said hafnium-based dielectric; and aSi-containing conductor located above said electrically conductingcapping layer, wherein said rare-earth-containing layer introduces viaelectronegativity differences a negative shift in threshold voltage. 2.The n-MOSFET material stack of claim 1 further comprising a chemox layerlocated beneath said Hf-based dielectric.
 3. The n-MOSFET material stackof claim 1 wherein said Hf-based dielectric comprises hafnium oxide,hafnium silicate, hafnium silicon oxynitride, a mixture of hafnium oxideand zirconium oxide or multilayers thereof.
 4. The n-MOSFET materialstack of claim 3 wherein said Hf-based dielectric comprises hafniumoxide.
 5. The n-MOSFET material stack of claim 1 wherein said Group IIIBelement is one of La, Ce, Y, Sm, Er and Tb.
 6. The n-MOSFET materialstack of claim 5 wherein said Group IIIB element is La and said rareearth metal-containing layer is La₂O₃ or LaN.
 7. The n-MOSFET materialstack of claim 1 wherein said electrically conductive capping layercomprises a metal nitride or metal silicon nitride, wherein said metalis from Group IVB or VB of the Periodic Table of Elements.
 8. Then-MOSFET material stack of claim 8 wherein said electrically conductivecapping layer comprises TiN, TaN, a ternary alloy of Ti—La—N, a ternaryalloy of Ta—La—N or a stack with a ternary alloy of Ti—La—N or Ta—La—Nwherein said rare earth metal-containing layer is present in saidelectrically conductive capping layer.
 9. The n-MOSFET material stack ofclaim 1 comprising an optional chemox layer, HfO₂ or Hf silicate as saidHf-based dielectric, a metal nitride layer including at least one rareearth metal or rare earth-like material, and polySi as the Si-containinggate conductor, wherein said metal nitride layer is used as both saidrare earth-containing layer and said electrically conducting cappinglayer.
 10. The n-MOSFET material stack of claim 1 comprising optionallya SiO₂ chemox layer, HfO₂ or Hf silicate as said Hf-based dielectric, aLa containing material as the rare earth metal-containing layer, TiN asthe electrically conductive capping layer, and n-doped Si as theSi-containing conductor.
 11. An n-MOSFET material stack comprising: ahafnium-based dielectric containing a concentration gradient of a rareearth metal comprising at least one element from Group IIIB of thePeriodic Table of Elements located atop of, or within, saidhafnium-based dielectric; an electrically conductive capping layerlocated above said hafnium-based dielectric; and a Si-containingconductor, wherein said rare-earth-containing metal introduces viaelectronegativity differences a negative shift in threshold voltage. 12.The n-MOSFET material stack of claim 11 further comprising a chemoxlayer located beneath said Hf-based dielectric.
 13. The n-MOSFETmaterial stack of claim 11 wherein said Hf-based dielectric compriseshafnium oxide, hafnium silicate, hafnium silicon oxynitride, a mixtureof hafnium oxide and zirconium oxide or multilayers thereof.
 14. Then-MOSFET material stack of claim 13 wherein said Hf-based dielectriccomprises hafnium oxide.
 15. The n-MOSFET material stack of claim 11wherein said Group IIIB element is one of La, Ce, Y, Sm, Er and Tb. 16.The n-MOSFET material stack of claim 15 wherein said Group IIIB elementis La.
 17. The n-MOSFET material stack of claim 11 wherein saidelectrically conductive capping layer comprises a metal nitride or metalsilicon nitride, wherein said metal is from Group IVB or VB of thePeriodic Table of Elements.
 18. The n-MOSFET material stack of claim 11comprising an optional chemox layer, HfO₂ or Hf silicate as saidHf-based dielectric, a metal nitride layer including at least one rareearth metal or rare earth-like metal, and polySi as the Si-containinggate conductor, wherein said metal nitride layer is used as both saidrare earth-containing metal and said electrically conducting cappinglayer.
 19. The n-MOSFET material stack of claim 11 comprising optionallya SiO₂ chemox layer, HfO₂ or Hf silicate as said Hf-based dielectric, aLa containing material as the rare earth metal-containing metal, TiN asthe electrically conductive capping layer, and n-doped Si as theSi-containing conductor.
 20. An n-MOSFET material stack comprising: ahafnium-based dielectric containing foreign atoms having a valence andelectronegativity different from hafnium located atop of, or within,said hafnium-based dielectric, said foreign atoms comprising a rareearth metal from Group IIIB of the Periodic Table of Elements; anelectrically capping layer located above said hafnium-based dielectric;and a Si-containing conductor, wherein said foreign atoms provide anegative shift in threshold voltage.
 21. The n-MOSFET material stack ofclaim 20 wherein said Hf-based dielectric comprises hafnium oxide,hafnium silicate, hafnium silicon oxynitride, a mixture of hafnium oxideand zirconium oxide or multilayers thereof.
 22. The n-MOSFET materialstack of claim 20 wherein said Hf-based dielectric comprises hafniumoxide.
 23. The n-MOSFET material stack of claim 20 wherein said GroupIIIB element is one of La, Ce, Y, Sm, Er and Tb.
 24. The n-MOSFETmaterial stack of claim 23 wherein said Group IIIB element is La.
 25. Asemiconductor structure comprising: a patterned n-MOSFET material stacklocated on a surface of a semiconductor substrate, said patternedn-MOSFET material stack comprising a hafnium-based dielectric; a rareearth-containing layer located on atop of, or within, said hafnium-baseddielectric; an electrically conductive capping layer located above saidhafnium-based dielectric; and a Si-containing conductor, wherein saidrare-earth-containing layer introduces electronegativity into saidhafnium-based dielectric to provide a negative shift in thresholdvoltage, and an alignment of a Fermi level of the Si-containingelectrode with a conduction band of said semiconductor substrate.